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1/14 STA515 july 2004 this is preliminary information on a new product now in development. details are subject to change without notice. 1 features multipower bcd technology minimum input output pulse width distortion 200m ? r dson complementary dmos output stage cmos compatible logic inputs thermal protection thermal warning output under voltage protection short circuit protection 2 description STA515 is a monolithic quad half bridge stage in mul- tipower bcd technology. the device can be used also as dual bridge or reconfigured, by connecting config pin to vdd pin, as single bridge with double current capability. the device is particularly designed to make the out- put stage of a stereo all-digital high efficiency (ddx?) amplifier capable to deliver an output power of 20w x 4 channels @ thd = 10% at v cc 26v on 4 ? load in single ended configuration. it can also deliver 40 + 40w @ thd = 10% at v cc 26v as output power on 8 ? load in btl configuration and 60w @ thd = 10% at v cc 32v on 8 ? in single paral- leled btl configuration. the input pins have thresh- old proportional to v l pin voltage. product preview 40v 3.0a quad power half bridge figure 2. audio application circuit ( quad single ended) l11 22 h l12 22 h c51 1 f c71 100nf c91 1 f c81 100nf c31 820 f c21 2200 f c58 100nf c58 100nf r57 10k r59 10k r41 20 r61 5k r62 5k r51 6 c53 100nf c60 100nf c61 100nf 15 m3 in1a in1a vl config pwrdn pwrdn fault tri-state th_war t h_war +3.3v in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in2a in1b in2a in2b protections & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 outpl pgnd1p outpl v cc 1p 14 12 10 11 outnl pgnd1n outnl v cc 1n 13 c52 1 f +v cc c62 100nf 7 m17 m15 m16 m14 8 9 outpr pgnd2p outpr v cc 2p 6 4 2 3 outnr pgnd2n d03au1474 outnr v cc 2n 5 19 31 20 gndsub 1 in2b 32 c72 100nf c92 1 f c82 100nf r52 6 c41 330pf r42 20 c42 330pf c32 820 f l13 22 h l14 22 h c73 100nf c93 1 f c83 100nf c33 820 f r43 20 r53 6 c74 100nf c94 1 f c84 100nf r54 6 c43 330pf r44 20 c44 330pf c34 820 f r63 5k r64 5k r65 5k r66 5k r67 5k r68 5k 4 ? 4 ? 4 ? 4 ? rev. 2 figure 1. package t able 1. order codes part number package STA515 psso36 (slug up) psso36 (slug up)
STA515 2/14 table 2. pin function n pin description 1 gnd-sub substrate ground 2 ; 3 out2b output half bridge 2b 4 vcc2b positive supply 5 gnd2b negative supply 6 gnd2a negative supply 7 vcc2a positive supply 8 ; 9 out2a output half bridge 2a 10 ; 11 out1b output half bridge 1b 12 vcc1b positive supply 13 gnd1b negative supply 14 gnd1a negative supply 15 vcc1a positive supply 16 ; 17 out1a output half bridge 1a 18 nc not connected 19 gnd-clean logical ground 20 gnd-reg ground for regulator vdd 21 ; 22 vdd 5v regulator referred to ground 23 vl logic reference voltage 24 config configuration pin 25 pwrdn stand-by pin 26 tri-state hi-z pin 27 fault fault pin advisor 28 th-war thermal warning advisor 29 in1a input of half bridge 1a 30 in1b input of half bridge 1b 31 in2a input of half bridge 2a 32 in2b input of half bridge 2b 33 ; 34 vss 5v regulator referred to +vcc 35 ; 36 vcc sign signal positive supply
3/14 STA515 table 3. functional pin status note: 1. the pin is open collector. to have the high logic value, it needs to be pulled up by a resistor. 2. to put config = 1 means connect pin 24 (config) to pins 21, 22 (vdd) to implemented single btl (mono mode) operation for high current. figure 3. pin connection pin name pin n. logical value ic -status fault 27 0 fault detected (short circuit, or thermal ..) fault * 27 1 normal operation tri-state 26 0 all powers in hi-z state tri-state 26 1 normal operation pwrdn 25 0 low consumption pwrdn 25 1 normal operation thwar 28 0 temperature of the ic =130c thwar (1) 28 1 normal operation config 24 0 normal operation config (2) 24 1 out1a=out1b ; out2a=out2b (if in1a = in1b; in2a = in2b) gnd-su b out2b out2b v cc 2b gnd1b v cc 1a gnd1a out1a out1a gnd-reg v dd v dd config v l v ss v ss v cc sign v cc sign 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 n.c. g nd-clean d01au1556 out1b v cc 1b out1b pwrdn fault t ri-state 9 8 7 28 29 30 out2a th_war 10 27 gnd2b out2a v cc 2a in1a in2b in1b 14 12 11 23 25 26 gnd2a in2a 13 24
STA515 4/14 table 4. absolute maximum ratings table 5. (*) recommended operating conditions (*) performances not guaranteed beyond recommended operating conditions table 6. thermal data (*) (*) see thermal information table 7. electrical characteristcs refer to circuit in fig.4 (v l = 3.3v; v cc = 30v; r l = 8 ?; fsw = 384khz; t amb = 25c unless otherwise specified) symbol parameter value unit v ce dc supply voltage (pin 4,7,12,15) 40 v v max maximum voltage on pins 23 to 32 5.5 v t op operating temperature range 0 to 70 c p tot power dissipation (tcase = 70c) 21 w t stg , t j storage and junction temperature -40 to 150 c symbol parameter min. typ. max. unit v cc dc supply voltage 10 36.0 v v l input logic reference 2.7 3.3 5.0 v t amb ambient temperature 0 70 c symbol parameter min. typ. max. unit t j-case thermal resistance junction to case (thermal pad) 1.5 c/w t jsd thermal shut-down junction temperature 150 c t warn thermal warning temperature 130 c t hsd thermal shut-down hysteresis 25 c symbol parameter test conditions min. typ. max. unit r dson power pchannel/nchannel mosfet rdson id=1a;t=25c 200 270 m ? i dss power pchannel/nchannel leakage idss vcc=35v;t=25c 50 a g n power pchannel rdson matching id=1a; t=25c 95 % g p power nchannel rdson matching id=1a; t=25c 95 % dt_s low current dead time (static) see test circuit no.4;t=25c 10 20 ns dt_d high current dead time (dinamic) l=22 h; c = 470nf; rl = 8 ? id=3.0a; t=25c; see fig. 6 50 ns t d on turn-on delay time resistive load; vcc=30v;t=25c 100 ns t d off turn-off delay time resistive load; vcc=30v;t=25c 100 ns t r rise time resistive load; as fig.4;t=25c 25 ns t f fall time resistive load; as fig. 4;t=25c 25 ns v cc supply voltage operating voltage 10 36 v v in-h high level input voltage v l /2 +300mv v
5/14 STA515 notes: 1. the following table explains the v low , v high variation with ibias note 2: see relevant application note an1994 table 8. logic truth table (see fig. 5) v in-l low level input voltage v l /2 - 300mv v i in-h hi level input current pin voltage = v l 1 a i in-l low level input current pin voltage = 0.3v 1 a i pwrdn-h hi level pwrdn pin input current v l = 3.3v 35 a v low low logical state voltage vlow (pin pwrdn, tristate) (note 1) v l = 3.3v 0.8 v v high high logical state voltage vhigh (pin pwrdn, tristate) (note 1) v l = 3.3v 1.7 v i vcc- pwrdn supply current from vcc in power down pwrdn = 0 3 ma i fault output current pins fault -th-warn when fault conditions vpin = 3.3v 1 ma i vcc-hiz supply current from vcc in tri- state vcc=30v; tri-state=0; t=25c 22 ma i vcc supply current from vcc in operation (both channel switching) vcc=30v; input pulse width = 50% duty; switching frequency = 384khz; no lc filters; 50 ma i vcc-q isc (short circuit current limit) (note 2) vcc = 30v;t = 25c 3.0 6 8 a i out-sh undervoltage protection threshold t = 25c 7 v v ov output minimum pulse width no load 70 150 ns v l v low min v high max unit 2.7 0.7 1.5 v 3.3 0.8 1.7 v 5 0.85 1.85 v tri-stateinxainxbq1q2q3q4 output mode 0 x x off off off off hi-z 1 0 0 off off on on dump 1 0 1 off on on off negative 1 1 0 on off off on positive 1 1 1 on on off off not used symbol parameter test conditions min. typ. max. unit table 7. electrical characteristcs (continued)
STA515 6/14 figure 4. test circuit. figure 5. figure 6. low current dead time = max(dtr,dtf) outxy vcc (3/4)vc c (1/2)vc c (1/4)vc c t dtf dtr d uty cycle = 50% inxy outxy gnd +vcc m58 m57 r 8 ? + - v67 = vdc = vcc/2 d03au1458 i nxa inx b +v cc q1 q3 q2 q4 outxa gnd outxb d00au1134 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=4.5a iout=4.5a q4 q1 q3 m64 inb m63 d03au1517 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4.5a in the direction shown in figure l68 22 l67 22 outa
7/14 STA515 3 technical info: the STA515 is a dual channel h-bridge that is able to deliver 40w per channel (@ thd=10% r l = 8 ? , v cc = 26v) of audio output power in high efficiency. the STA515 converts both ddx and binary-controlled pwm signals into audio power at the load. it includes a logic interface , integrated bridge drivers, high efficiency mosfet outputs and thermal and short circuit protec- tion circuitry. in ddx mode, two logic level signals per channel are used to control high-speed mosfet switches to connect the speaker load to the input supply or to ground in a bridge configuration, according to the damped ternary modulation operation. in binary mode operation , both full bridge and half bridge modes are supported. the STA515 includes over- current and thermal protection as well as an under-voltage lockout with automatic recovery. a thermal warning status is also provided. figure 7. STA515 block diagram full-bridge ddx ? or binary modes figure 8. STA515 block diagram binary half-bridge mode 3.1 logic interface and decode: the STA515 power outputs are controlled using one or two logic level timing signals. in order to provide a proper logic interface, the vbias input must operate at the dame voltage as the ddx control logic supply. 3.2 protection circuitry: the STA515 includes protection circuitry for over-current and thermal overload conditions. a thermal warning pin (pin.28) is activated low (open drain mosfet) when the ic temperature exceeds 130c, in advance of the thermal shutdown protection. when a fault condition is detected , an internal fault signal acts to immediately disable the output power mosfets, placing both h-bridges in high impedance state. at the same time an open- drain mosfet connected to the fault pin (pin.27) is switched on. there are two possible modes subsequent to activating a fault: logic i/f and decode left h-bridge protection circuitry inl[1:2] inr[1:2] pwrdn outpl fault vl tri-state outnl outpr outnr twarn regulators right h-bridge logic i/f and decode lefta ?-bridge protection circuitry inl[1:2] inr[1:2] pwrdn outpl fault vl tri-state outnl outpr outnr twarn regulators righta ?-bridge leftb ?-bridge rightb ?-bridge
STA515 8/14 ? 1) shutdown mode : with fault (pull-up resistor) and tri-state pins independent, an activated fault will disable the device, signaling low at the fault output. the device may subsequently be reset to normal operation by toggling the tri-state pin from high to low to high using an external logic signal. ? 2) automatic recovery mode: this is shown in the audio application circuit of quad single end- ed). the fault and tri-state pins are shorted together and connected to a time constant circuit comprising r59 and c58. an activated fault will force a reset on the tri-state pin causing normal operation to resume fol- lowing a delay determined by the time constant of the circuit. if the fault condition is still present , the circuit operation will continue repeating until the fault condition is removed . an increase in the time constant of the circuit will produce a longer recovery interval. care must be taken in the overall system design as not to exceed the protection thesholds under normal operation. 3.3 power outputs: the STA515 power and output pins are duplicated to provide a low impedance path for the device's bridged outputs . all duplicate power, ground and output pins must be connected for proper operation. the pwrdn or tri-state pins should be used to set all mosfets to the hi-z state during power-up until the logic power supply, v l , is settled. 3.4 parallel output / high current operation: when using ddx mode output , the STA515 outputs can be connected in parallel in order to increase the output current capability to a load. in this configuration the STA515 can provide 60w into 8 ohm. this mode of operation is enabled with the config pin (pin.24) connected to vreg1 and the inputs combined inla=inlb, inra=inrb and the outputs combined outla=otlb, outra=outrb. 3.5 additional informations: output filter: a passive 2nd-order passive filter is used on the STA515 power outputs to reconstruct an analog audio signal . system performance can be significantly affected by the output filter design and choice of passive components. a filter design for 6ohm/8ohm loads is shown in the typical application circuit of fig.10. quad single ended circuit (page 1) shows a filter for ? bridge mode, 4 ohm loads.
9/14 STA515 figure 9. typical stereo full bridge configuration to obtain 40+40w @ thd = 10%, r l = 8 ? , v cc = 26v figure 10. typical single btl configuration to obtain 60w @ thd 10%, r l = 8 ? , v cc = 32v (note 1)) note: 1. "a pwm modulator as driver is needed . in particular, this result is performed using the sta308+STA515+sta50x demo board ". peak power for t 1sec l18 22 h l19 22 h c30 1 f c20 100nf c99 100nf c101 100nf c107 100nf c106 100nf c23 470nf c55 1000 f c21 100nf c58 100nf c58 100nf r57 10k r59 10k r63 20 r98 6 r100 6 c53 100nf c60 100nf c31 1 f c52 330pf r104 20 c109 330pf 15 m3 in1a in1a vl config pwrdn pwrdn fault tri-state th_war t h_war +3.3v in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in2a in1b in2a in2b protections & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 out1a gnd1a out1a v cc 1a 14 12 10 11 out1b gnd1b out1b v cc 1b 13 l113 22 h l112 22 h c32 1 f +v cc c108 470nf c33 1 f 7 m17 m15 m16 m14 8 9 out2a gnd2a out2a v cc 2a 6 4 2 3 out2b gnd2b d00au1148b out2b v cc 2b 5 19 31 20 gndsub 1 in2b 32 c110 100nf c111 100nf r103 6 r102 6 8 ? 8 ? 22 h 22 h 100nf film 100nf x7r 100nf x7r 1 f x7r 2200 f 63v 470nf film 100nf film 100nf 10k 10k 6.2 1/2w 6.2 1/2w 100nf x7r 100nf x7r add. in1a in1a vl config pwrdn npwrdn fault tri-state th_war t h_war +3.3v 100nf 100nf x7r in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in1b in2a 29 23 n.c. 24 25 27 26 28 30 21 22 33 34 35 36 17 16 18 out1a gnd1b out1a v cc 1b 10 13 11 out1b gnd1a out1b 14 32v 330pf 22 ? 1/2w 8 ? gnd2a 6 2 12 v cc 1a 15 v cc 2b 4 v cc 2a 7 3 out2b gnd2b d04au1549 out2b 5 19 31 20 gndsub 1 in2b 32 8 9 out2a out2a 1 f x7r 32v
STA515 10/14 4 thermal information: the power dissipated within the device depends primarly on the supply voltage, load impedance and output modulation level. the psso36 package of the STA515 includes an exposed thermal slug on the top of the device to provide a direct thermal path from the ic to the heatsink. for the quad single ended application the dissipated power vs ouptut power is shown in fig.11 considering that for the STA515 the thermal resistance junction to slug is 1.5c/w and the extimated thermal resistance due to the grease placed between slug and heat sink is 2.3c/w ( the use of thermal pads for this package is not recommended), the suitable heat sink rth to be used can be drawn from the following graph fig 12, where is shown the derating power vs.tambient for different heatsinkers. 5 characterization curves 5.1 the following characterization are obtained using the quad single ended configuration (fig.2) with sta308a controller figure 11. power dissipation vs output power figure 12. power derating curve figure 13. thd+n vs output power figure 14. output power vs supply voltage 0 2 4 6 8 10 12 14 0 5 10 15 20 vcc=26v rl= 4ohm f =1khz pd (w) 4 x pout (w) 5 10 15 20 25 0 20 40 60 80 100 120 140 16 0 pd(w) tambient(c) 1)infinite 2) 1.5 c/w 3) 3 c/w 4) 4.5 c/w 5) 6 c/w 2 3 1 4 5 5 10 15 20 25 0 20 40 60 80 100 120 140 16 0 pd(w) tambient(c) 1)infinite 2) 1.5 c/w 3) 3 c/w 4) 4.5 c/w 5) 6 c/w 2 3 1 4 5 0.1 10 0.2 0.5 1 2 5 t hd(%) 100m 3 0 200m 500m 1 2 5 10 20 pout(w) vcc = 26v rl = 4 ohm f = 1khz single ended 2.5 30 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 p out(w) +10 + 30 +12 +14 +16 +18 +20 +22 +24 +26 +28 vdc rl=4 ohm f=1khz single ended thd=10% thd=1% 2.5 30 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 p out(w) +10 + 30 +12 +14 +16 +18 +20 +22 +24 +26 +28 vdc rl=4 ohm f=1khz single ended thd=10% thd=1%
11/14 STA515 figure 15. thd vs frequency 5.2 the following characterizations are obtained using the stereo full bridge configuration (fig. 9) with sta308a controller figure 16. output power vs supply voltage figure 17. thd+n vs output power figure 18. power dissipation vs output power 5.3 the following characterizations are obtained using the single btl configuration (fig. 10) with sta308a controller figure 19. thd+n vs output power 0.01 1 0.02 0.05 0.1 0.2 0.5 t hd(%) 20 2 0k 50 100 200 500 1k 2k 5k 10k freq(hz) rl =4 ohm pout=1w single ended 0.01 1 0.02 0.05 0.1 0.2 0.5 t hd(%) 20 2 0k 50 100 200 500 1k 2k 5k 10k freq(hz) rl =4 ohm pout=1w single ended 0 70 5 10 15 20 25 30 35 40 45 50 55 60 65 po(w) +10 +3 2 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 vsupply (v) rl=8 ohm f = 1khz thd=10% thd=1% stereo full btl single parallelbtl 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 100m 5 0 200m 500m 1 2 5 10 20 t hd(%) pout(w) vcc= 26v rl=8 ohm f = 1khz double btl 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35 40 pd (w) 2 x pout (w) vcc=26v rl=8ohm f=1khz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 100m 8 0 200m 500m 1 2 5 10 20 50 pout(w) t hd(%) vcc=32v rl=8ohm f=1khz single btl
STA515 12/14 figure 20. powersso-36 (slug up) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.15 2.47 0.084 0.097 a2 2.15 2.40 0.084 0.094 a1 0 0.075 0 0.003 b 0.18 0.36 0.007 0.014 c 0.23 0.32 0.009 0.012 d (1) 10.10 10.50 0.398 0.413 e (1) 7.4 7.6 0.291 0.299 e0.50 0.020 e3 8.50 0.035 f 2.3 0.090 g 0.10 0.004 g1 0.06 0.002 h 10.10 10.50 0.398 0.413 h 0.40 0.016 l 0.55 0.85 0.022 0.033 m 4.3 0.169 n 10? (max) o 1.2 0.047 q 0.8 0.031 s 2.9 0.114 t3.65 0.144 u 1.0 0.039 x 4.10 4.70 0.161 0.185 y 6.50 7.10 0.256 0.279 (1) ?d and e? do not include mold flash or protusions. mold flash or protusions shall not exceed 0.15mm (0.006?) (2) no intrusion allowed inwards the leads. (3) flash or bleeds on exposed die pad shall not exceed 0.4 mm per side 7618147 a powersso-36 (slug-up)
13/14 STA515 table 9. revision history date revision description of changes may 2004 1 first issue july 2004 2 small change
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ddx is a trademark of apogee tecnology inc. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 14/14 STA515

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